1. Field of the Invention
The present invention relates to three dimensional (3D) packaging, and more particularly to the integration of through-silicon vias (TSVs) into 3D packages.
2. Discussion of Related Art
3D packaging is emerging as a solution for microelectronics development toward system on chip (SOC) and system in package (SIP). In particular, 3D flip chip structures with TSVs have the potential for being widely adopted. TSV 3D packages generally contain two or more chips stacked vertically, with vias through silicon substrates replacing edge wiring to create an electrical connection between the circuit elements on each chip.
The Joint Electron Devices Engineering Council (JEDEC) is currently developing a WideIO standard defining the chip-to-chip landing pad interface for a logic-to-memory interface. Conventionally, the physical locations of TSVs are located directly beneath the landing pad locations on a chip, which takes up a lot of real estate. This means that all other circuitry is laid out around the TSV locations.
During TSV processing, the array of TSVs are formed through a thinned device wafer. Conventional TSV structures use either silicon dioxide or polymers as an insulator material on the backside of the thinned device wafer. These materials are not hermetic, and do not provide a robust passivation layer on the backside of the thinned device wafer.